1. Field of the Invention
This invention relates to semiconductor fabrication technologies, and more particularly, to a bonding-pad structure for integrated circuit and a method of fabricating the same, which allows the bonding pads on the IC chip to be arranged at any locations on the surface of the IC chip.
2. Description of Related Art
The manufacturing process for integrated circuits (IC) includes three stages: wafer preparation, integrated circuit fabrication, and packaging. A wafer is a round piece of a semiconductor material which is subdivided into a number of dies on each of which one IC unit is fabricated. In the case of fabricating a VLSI (very large-scale integration) IC chip with a line width of 0.25 .mu.m (micrometer), for example, it requires a wafer of a diameter of 8 in (200 mm), which is subdivided into a total of more than 200 dies, each being about 2 cm.sup.2 in size. After circuit components are formed into the wafer, each of these dies is then cut apart from the fabricated wafer (Note that in semiconductor terminology, a die cut apart from the fabricated wafer is then referred to as a chip). Each chip is then packaged in a hermetically sealed compound to form a complete IC package. The fabrication and packaging of the IC chip is typically a very complex process and requires state-of-the-art technologies to achieve. The basic steps of a typical manufacturing process for an IC package are briefly depicted in the following with reference to FIGS. 1A-1D.
Referring first to FIG. 1A, a fabricated wafer 10 includes a number of dies 12, each being a single IC unit that is then cut apart from the wafer 10 (each cut-apart die is then referred to as a chip). Referring next to FIG. 1B, in the subsequent step, each chip 12 is mounted on a leadframe 14 having a plurality of pins 16. Referring further to FIG. 1C, a wire-bonding process is then performed so as to connect a plurality of conductive wires 18 between the bonding pads (not shown) on the chip 12 and the pins 16 on the leadframe 14. Referring next to FIG. 1D, a resin compound 19 is then formed to hermetically seal the chip 12 therein. This completes the packaging of the chip 12. In the foregoing manufacturing process for the IC package, various methods can be used for the packaging of the IC chip, such as TAB, PGA, and BGA, to name a few.
An IC chip is customarily formed with a plurality of bonding pads on the surface thereof, which can be connected via wires to the pins on the leadframe through a wire bonding process. This allows the internal circuit of the IC chip to be later electrically connected to external circuitry via the pins. A conventional bonding-pad structure is illustratively depicted in the following with reference to FIGS. 2A-2B.
As shown in FIG. 2A, an IC chip 20 is typically subdivided into an internal-circuit area 22 where the various circuit components (not shown) of the IC chip are formed, and a peripheral area 24 where a plurality of bonding pads 26 are formed. These bonding pads 26 are structured in the same manner. The structure of each of the bonding pads 26 is depicted in the following with reference to FIG. 2B.
FIG. 2B shows a schematic cross-sectional view of the part of the IC chip 20 of FIG. 2A that is enclosed by a dashed box indicated by the reference numeral 25, i.e., the bonding-pad structure of one of the bonding pads 26. As shown, the bonding-pad structure comprises an insulating layer 27, such as an oxide layer; and a multi-layer metallization structure formed over the insulating layer 27, including a first metallization layer 29a, a second metallization layer 29b, a third metallization layer 29c, and a fourth metallization layer 29d. Further, a multi-layer insulation structure is formed around the multi-layer metallization structure for insulation purpose, which includes a first insulating layer 28a, a second insulating layer 28b, and a third insulating layer 28c.
One drawback to the foregoing conventional bonding-pad structure, however, is that it is a low-integration structure that may be unsuited to more advanced technologies with higher integration. Moreover, since the conventional bonding-pad structure can be formed only in the peripheral area 24 of the IC chip 20, the peripheral area 24 will be very large when a large number of bonding pads are formed. In this case, the overall size of the IC chip 20 will be considerably large.